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Support R_AARCH64_ADR_PREL_PG_HI21_NC

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This commit is contained in:
Peter Collingbourne 2023-07-26 21:33:26 -07:00
parent de991b519a
commit 17a5c3e0ab
1 changed files with 5 additions and 2 deletions
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7
elf/arch-arm64.cc
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@ -232,7 +232,8 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
i++;
}
break;
case R_AARCH64_ADR_PREL_PG_HI21: {
case R_AARCH64_ADR_PREL_PG_HI21:
case R_AARCH64_ADR_PREL_PG_HI21_NC: {
// The ARM64 psABI defines that an `ADRP x0, foo` and `ADD x0, x0,
// :lo12: foo` instruction pair to materialize a PC-relative address
// in a register can be relaxed to `NOP` followed by `ADR x0, foo`
@ -259,7 +260,8 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
}
i64 val = page(S + A) - page(P);
check(val, -(1LL << 32), 1LL << 32);
if (rel.r_type == R_AARCH64_ADR_PREL_PG_HI21)
check(val, -(1LL << 32), 1LL << 32);
write_adrp(loc, val);
break;
}
@ -519,6 +521,7 @@ void InputSection<E>::scan_relocations(Context<E> &ctx) {
sym.flags |= NEEDS_GOTTP;
break;
case R_AARCH64_ADR_PREL_PG_HI21:
case R_AARCH64_ADR_PREL_PG_HI21_NC:
scan_pcrel(ctx, sym, rel);
break;
case R_AARCH64_TLSGD_ADR_PAGE21: