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Use defined functions to generate TH for ARM
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@ -21,7 +21,7 @@ import qualified Data.Macaw.Types as MT
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import Data.Proxy ( Proxy(..) )
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import Dismantle.ARM -- must be present to supply definitions for genExecInstruction output
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import qualified SemMC.Architecture.AArch32 as ARMSem
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import SemMC.Architecture.ARM.Opcodes ( allA32Semantics, allA32OpcodeInfo )
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import SemMC.Architecture.ARM.Opcodes ( allA32Semantics, allA32OpcodeInfo, a32DefinedFunctions )
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execInstruction :: MC.Value ARMSem.AArch32 ids (MT.BVType 32)
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@ -34,5 +34,6 @@ execInstruction = $(genExecInstructionLogStdErr (Proxy @ARMSem.AArch32)
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'a32InstructionMatcher
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allA32Semantics
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allA32OpcodeInfo
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a32DefinedFunctions
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([t| Dismantle.ARM.Operand |], [t| ARMSem.AArch32 |])
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)
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@ -62,7 +62,7 @@ armNonceAppEval bvi nonceApp =
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S.FnApp symFn args ->
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let nm = symFnName symFn
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in case nm of
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"arm_is_r15" -> return $
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"uf_arm_is_r15" -> return $
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-- This requires special handling because this can
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-- be checking actual GPR locations or the results
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-- of an expression extracting a register number
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@ -21,7 +21,7 @@ import qualified Data.Macaw.Types as MT
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import Data.Proxy ( Proxy(..) )
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import Dismantle.Thumb -- as ThumbDis -- must be present to supply definitions for genExecInstruction output
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import qualified SemMC.Architecture.AArch32 as ARMSem
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import SemMC.Architecture.ARM.Opcodes ( allT32Semantics, allT32OpcodeInfo )
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import SemMC.Architecture.ARM.Opcodes ( allT32Semantics, allT32OpcodeInfo, t32DefinedFunctions )
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execInstruction :: MC.Value ARMSem.AArch32 ids (MT.BVType 32)
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@ -34,5 +34,6 @@ execInstruction = $(genExecInstructionLogStdErr (Proxy @ARMSem.AArch32)
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't32InstructionMatcher
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allT32Semantics
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allT32OpcodeInfo
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t32DefinedFunctions
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([t| Dismantle.Thumb.Operand |], [t| ARMSem.AArch32 |])
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)
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