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Kernel: Add bar_address_mask to mask the last 4 bits of a BAR address
Create a bar_address_mask constant to mask the last 4 bits of a BAR address instead of hand coding the mask all over the kernel.
This commit is contained in:
parent
20d517f1da
commit
83b87a5ade
Notes:
sideshowbarker
2024-07-17 00:37:23 +09:00
Author: https://github.com/Panky-codes 🔰 Commit: https://github.com/SerenityOS/serenity/commit/83b87a5ade Pull-request: https://github.com/SerenityOS/serenity/pull/18484 Reviewed-by: https://github.com/gmta ✅
@ -227,7 +227,7 @@ size_t get_BAR_space_size(DeviceIdentifier const& identifier, HeaderType0BaseReg
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write32_offsetted(identifier, field, 0xFFFFFFFF);
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write32_offsetted(identifier, field, 0xFFFFFFFF);
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u32 space_size = read32_offsetted(identifier, field);
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u32 space_size = read32_offsetted(identifier, field);
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write32_offsetted(identifier, field, bar_reserved);
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write32_offsetted(identifier, field, bar_reserved);
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space_size &= 0xfffffff0;
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space_size &= bar_address_mask;
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space_size = (~space_size) + 1;
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space_size = (~space_size) + 1;
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return space_size;
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return space_size;
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}
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}
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@ -240,7 +240,7 @@ size_t get_expansion_rom_space_size(DeviceIdentifier const& identifier)
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write32_offsetted(identifier, field, 0xFFFFFFFF);
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write32_offsetted(identifier, field, 0xFFFFFFFF);
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u32 space_size = read32_offsetted(identifier, field);
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u32 space_size = read32_offsetted(identifier, field);
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write32_offsetted(identifier, field, bar_reserved);
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write32_offsetted(identifier, field, bar_reserved);
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space_size &= 0xfffffff0;
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space_size &= bar_address_mask;
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space_size = (~space_size) + 1;
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space_size = (~space_size) + 1;
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return space_size;
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return space_size;
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}
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}
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@ -78,6 +78,7 @@ static constexpr u16 value_port = 0xcfc;
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static constexpr size_t mmio_device_space_size = 4096;
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static constexpr size_t mmio_device_space_size = 4096;
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static constexpr u16 none_value = 0xffff;
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static constexpr u16 none_value = 0xffff;
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static constexpr size_t memory_range_per_bus = mmio_device_space_size * to_underlying(Limits::MaxFunctionsPerDevice) * to_underlying(Limits::MaxDevicesPerBus);
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static constexpr size_t memory_range_per_bus = mmio_device_space_size * to_underlying(Limits::MaxFunctionsPerDevice) * to_underlying(Limits::MaxDevicesPerBus);
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static constexpr u32 bar_address_mask = 0xfffffff0;
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// Taken from https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf
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// Taken from https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf
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enum class ClassID {
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enum class ClassID {
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@ -56,16 +56,16 @@ UNMAP_AFTER_INIT ErrorOr<void> BochsGraphicsAdapter::initialize_adapter(PCI::Dev
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#if ARCH(X86_64)
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#if ARCH(X86_64)
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bool virtual_box_hardware = (pci_device_identifier.hardware_id().vendor_id == 0x80ee && pci_device_identifier.hardware_id().device_id == 0xbeef);
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bool virtual_box_hardware = (pci_device_identifier.hardware_id().vendor_id == 0x80ee && pci_device_identifier.hardware_id().device_id == 0xbeef);
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if (pci_device_identifier.revision_id().value() == 0x0 || virtual_box_hardware) {
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if (pci_device_identifier.revision_id().value() == 0x0 || virtual_box_hardware) {
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m_display_connector = BochsDisplayConnector::must_create(PhysicalAddress(PCI::get_BAR0(pci_device_identifier) & 0xfffffff0), bar0_space_size, virtual_box_hardware);
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m_display_connector = BochsDisplayConnector::must_create(PhysicalAddress(PCI::get_BAR0(pci_device_identifier) & PCI::bar_address_mask), bar0_space_size, virtual_box_hardware);
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} else {
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} else {
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auto registers_mapping = TRY(Memory::map_typed_writable<BochsDisplayMMIORegisters volatile>(PhysicalAddress(PCI::get_BAR2(pci_device_identifier) & 0xfffffff0)));
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auto registers_mapping = TRY(Memory::map_typed_writable<BochsDisplayMMIORegisters volatile>(PhysicalAddress(PCI::get_BAR2(pci_device_identifier) & PCI::bar_address_mask)));
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VERIFY(registers_mapping.region);
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VERIFY(registers_mapping.region);
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m_display_connector = QEMUDisplayConnector::must_create(PhysicalAddress(PCI::get_BAR0(pci_device_identifier) & 0xfffffff0), bar0_space_size, move(registers_mapping));
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m_display_connector = QEMUDisplayConnector::must_create(PhysicalAddress(PCI::get_BAR0(pci_device_identifier) & PCI::bar_address_mask), bar0_space_size, move(registers_mapping));
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}
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}
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#else
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#else
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auto registers_mapping = TRY(Memory::map_typed_writable<BochsDisplayMMIORegisters volatile>(PhysicalAddress(PCI::get_BAR2(pci_device_identifier) & 0xfffffff0)));
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auto registers_mapping = TRY(Memory::map_typed_writable<BochsDisplayMMIORegisters volatile>(PhysicalAddress(PCI::get_BAR2(pci_device_identifier) & PCI::bar_address_mask)));
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VERIFY(registers_mapping.region);
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VERIFY(registers_mapping.region);
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m_display_connector = QEMUDisplayConnector::must_create(PhysicalAddress(PCI::get_BAR0(pci_device_identifier) & 0xfffffff0), bar0_space_size, move(registers_mapping));
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m_display_connector = QEMUDisplayConnector::must_create(PhysicalAddress(PCI::get_BAR0(pci_device_identifier) & PCI::bar_address_mask), bar0_space_size, move(registers_mapping));
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#endif
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#endif
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// Note: According to Gerd Hoffmann - "The linux driver simply does
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// Note: According to Gerd Hoffmann - "The linux driver simply does
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@ -47,8 +47,8 @@ ErrorOr<void> IntelNativeGraphicsAdapter::initialize_adapter()
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dmesgln_pci(*this, "framebuffer @ {}", PhysicalAddress(PCI::get_BAR2(device_identifier())));
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dmesgln_pci(*this, "framebuffer @ {}", PhysicalAddress(PCI::get_BAR2(device_identifier())));
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using MMIORegion = IntelDisplayConnectorGroup::MMIORegion;
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using MMIORegion = IntelDisplayConnectorGroup::MMIORegion;
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MMIORegion first_region { MMIORegion::BARAssigned::BAR0, PhysicalAddress(PCI::get_BAR0(device_identifier()) & 0xfffffff0), bar0_space_size };
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MMIORegion first_region { MMIORegion::BARAssigned::BAR0, PhysicalAddress(PCI::get_BAR0(device_identifier()) & PCI::bar_address_mask), bar0_space_size };
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MMIORegion second_region { MMIORegion::BARAssigned::BAR2, PhysicalAddress(PCI::get_BAR2(device_identifier()) & 0xfffffff0), bar2_space_size };
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MMIORegion second_region { MMIORegion::BARAssigned::BAR2, PhysicalAddress(PCI::get_BAR2(device_identifier()) & PCI::bar_address_mask), bar2_space_size };
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PCI::enable_bus_mastering(device_identifier());
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PCI::enable_bus_mastering(device_identifier());
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PCI::enable_io_space(device_identifier());
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PCI::enable_io_space(device_identifier());
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@ -69,7 +69,7 @@ UNMAP_AFTER_INIT ErrorOr<void> VMWareGraphicsAdapter::initialize_fifo_registers(
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{
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{
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auto framebuffer_size = read_io_register(VMWareDisplayRegistersOffset::FB_SIZE);
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auto framebuffer_size = read_io_register(VMWareDisplayRegistersOffset::FB_SIZE);
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auto fifo_size = read_io_register(VMWareDisplayRegistersOffset::MEM_SIZE);
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auto fifo_size = read_io_register(VMWareDisplayRegistersOffset::MEM_SIZE);
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auto fifo_physical_address = PhysicalAddress(PCI::get_BAR2(device_identifier()) & 0xfffffff0);
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auto fifo_physical_address = PhysicalAddress(PCI::get_BAR2(device_identifier()) & PCI::bar_address_mask);
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dbgln("VMWare SVGA @ {}: framebuffer size {} bytes, FIFO size {} bytes @ {}", device_identifier().address(), framebuffer_size, fifo_size, fifo_physical_address);
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dbgln("VMWare SVGA @ {}: framebuffer size {} bytes, FIFO size {} bytes @ {}", device_identifier().address(), framebuffer_size, fifo_size, fifo_physical_address);
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if (framebuffer_size < 0x100000 || fifo_size < 0x10000) {
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if (framebuffer_size < 0x100000 || fifo_size < 0x10000) {
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@ -185,7 +185,7 @@ UNMAP_AFTER_INIT ErrorOr<void> VMWareGraphicsAdapter::initialize_adapter()
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auto bar1_space_size = PCI::get_BAR_space_size(device_identifier(), PCI::HeaderType0BaseRegister::BAR1);
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auto bar1_space_size = PCI::get_BAR_space_size(device_identifier(), PCI::HeaderType0BaseRegister::BAR1);
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m_display_connector = VMWareDisplayConnector::must_create(*this, PhysicalAddress(PCI::get_BAR1(device_identifier()) & 0xfffffff0), bar1_space_size);
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m_display_connector = VMWareDisplayConnector::must_create(*this, PhysicalAddress(PCI::get_BAR1(device_identifier()) & PCI::bar_address_mask), bar1_space_size);
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TRY(m_display_connector->set_safe_mode_setting());
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TRY(m_display_connector->set_safe_mode_setting());
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return {};
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return {};
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}
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}
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@ -101,7 +101,7 @@ ErrorOr<NonnullOwnPtr<IOWindow>> IOWindow::create_for_pci_device_bar(PCI::Device
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return Error::from_errno(EOVERFLOW);
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return Error::from_errno(EOVERFLOW);
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if (pci_bar_space_type == PCI::BARSpaceType::Memory64BitSpace && Checked<u64>::addition_would_overflow(pci_bar_value, space_length))
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if (pci_bar_space_type == PCI::BARSpaceType::Memory64BitSpace && Checked<u64>::addition_would_overflow(pci_bar_value, space_length))
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return Error::from_errno(EOVERFLOW);
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return Error::from_errno(EOVERFLOW);
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auto memory_mapped_range = TRY(Memory::adopt_new_nonnull_own_typed_mapping<u8 volatile>(PhysicalAddress(pci_bar_value & 0xfffffff0), space_length, Memory::Region::Access::ReadWrite));
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auto memory_mapped_range = TRY(Memory::adopt_new_nonnull_own_typed_mapping<u8 volatile>(PhysicalAddress(pci_bar_value & PCI::bar_address_mask), space_length, Memory::Region::Access::ReadWrite));
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return TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOWindow(move(memory_mapped_range))));
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return TRY(adopt_nonnull_own_or_enomem(new (nothrow) IOWindow(move(memory_mapped_range))));
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}
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}
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@ -40,7 +40,7 @@ UNMAP_AFTER_INIT ErrorOr<void> NVMeController::initialize(bool is_queue_polled)
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PCI::enable_memory_space(device_identifier());
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PCI::enable_memory_space(device_identifier());
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PCI::enable_bus_mastering(device_identifier());
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PCI::enable_bus_mastering(device_identifier());
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m_bar = PCI::get_BAR0(device_identifier()) & BAR_ADDR_MASK;
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m_bar = PCI::get_BAR0(device_identifier()) & PCI::bar_address_mask;
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static_assert(sizeof(ControllerRegister) == REG_SQ0TDBL_START);
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static_assert(sizeof(ControllerRegister) == REG_SQ0TDBL_START);
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static_assert(sizeof(NVMeSubmission) == (1 << SQ_WIDTH));
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static_assert(sizeof(NVMeSubmission) == (1 << SQ_WIDTH));
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@ -34,8 +34,6 @@ struct IdentifyNamespace {
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u64 rsvd3[488];
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u64 rsvd3[488];
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};
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};
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// BAR
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static constexpr u32 BAR_ADDR_MASK = 0xFFFFFFF0;
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// DOORBELL
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// DOORBELL
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static constexpr u32 REG_SQ0TDBL_START = 0x1000;
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static constexpr u32 REG_SQ0TDBL_START = 0x1000;
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static constexpr u32 REG_SQ0TDBL_END = 0x1003;
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static constexpr u32 REG_SQ0TDBL_END = 0x1003;
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