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Add missing symmetric cases to dependentActions
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@ -329,11 +329,13 @@ dependentActions memtype buf a1 a2 = case (a1, a2) of
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-- a relaxed memory model, as an unsynchronised write gives rise to
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-- a commit, which synchronises.
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(UnsynchronisedRead r1, UnsynchronisedWrite r2) -> r1 == r2
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(UnsynchronisedWrite r1, UnsynchronisedRead r2) -> r1 == r2
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(UnsynchronisedWrite r1, UnsynchronisedWrite r2) -> r1 == r2
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-- Unsynchronised reads where a memory barrier would flush a
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-- buffered write
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(UnsynchronisedRead r1, _) | isBarrier a2 -> isBuffered buf r1 && memtype /= SequentialConsistency
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(_, UnsynchronisedRead r2) | isBarrier a1 -> isBuffered buf r2 && memtype /= SequentialConsistency
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(_, _)
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-- Two actions on the same CRef where at least one is synchronised
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