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4 Commits
de991b519a
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b0b015bc2e
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b0b015bc2e | ||
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7f66689e21 | ||
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17a5c3e0ab | ||
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3ed5b8ddf7 |
@ -442,6 +442,9 @@ if(NOT CMAKE_SKIP_INSTALL_RULES)
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if(EXISTS "${CMAKE_SOURCE_DIR}/LICENSE")
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install(FILES LICENSE DESTINATION ${CMAKE_INSTALL_DOCDIR})
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endif()
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if(EXISTS "${CMAKE_SOURCE_DIR}/LICENSE.third-party")
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install(FILES "LICENSE.third-party" DESTINATION "${CMAKE_INSTALL_DOCDIR}")
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endif()
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function(mold_install_relative_symlink OLD NEW)
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install(CODE "
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@ -232,7 +232,8 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
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i++;
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}
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break;
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case R_AARCH64_ADR_PREL_PG_HI21: {
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case R_AARCH64_ADR_PREL_PG_HI21:
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case R_AARCH64_ADR_PREL_PG_HI21_NC: {
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// The ARM64 psABI defines that an `ADRP x0, foo` and `ADD x0, x0,
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// :lo12: foo` instruction pair to materialize a PC-relative address
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// in a register can be relaxed to `NOP` followed by `ADR x0, foo`
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@ -259,7 +260,8 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
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}
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i64 val = page(S + A) - page(P);
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check(val, -(1LL << 32), 1LL << 32);
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if (rel.r_type == R_AARCH64_ADR_PREL_PG_HI21)
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check(val, -(1LL << 32), 1LL << 32);
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write_adrp(loc, val);
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break;
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}
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@ -519,6 +521,7 @@ void InputSection<E>::scan_relocations(Context<E> &ctx) {
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sym.flags |= NEEDS_GOTTP;
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break;
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case R_AARCH64_ADR_PREL_PG_HI21:
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case R_AARCH64_ADR_PREL_PG_HI21_NC:
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scan_pcrel(ctx, sym, rel);
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break;
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case R_AARCH64_TLSGD_ADR_PAGE21:
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