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Kernel/riscv64: Only enable interrupts in trap handler if they were on
Always enabling interrupts is in hindsight obviously a bug, as trapping code that has interrupts disabled very likely expects that they stay disabled.
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sideshowbarker
2024-07-17 06:40:35 +09:00
Author: https://github.com/spholz Commit: https://github.com/SerenityOS/serenity/commit/1a312f4265 Pull-request: https://github.com/SerenityOS/serenity/pull/23387 Reviewed-by: https://github.com/ADKaster ✅
@ -60,7 +60,8 @@ extern "C" void trap_handler(TrapFrame& trap_frame)
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// Exception
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// Exception
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Processor::current().enter_trap(trap_frame, false);
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Processor::current().enter_trap(trap_frame, false);
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Processor::enable_interrupts();
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if (trap_frame.regs->sstatus.SPIE == 1)
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Processor::enable_interrupts();
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using enum RISCV64::CSR::SCAUSE;
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using enum RISCV64::CSR::SCAUSE;
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switch (scause) {
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switch (scause) {
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